• 3-slot mainframe with USB, LAN and GPIB interfaces
• 6 1/2-digit (22-bit) internal DMM, scanning up to 450 channels per second with new solid-state multiplexer module
• 9 switch and control plug-in modules to choose from
• 24-bit sampling rate of 800 kSa/s with a new DAQM909A 4 channel digitizer module
• Built-in signal conditioning measures thermocouples, RTDs and thermistors, AC/DC volts and current; resistance, frequency/period, diode test and capacitance
• 100k readings of non-volatile memory holds data when power is removed
• Hi/LO alarm limits on each channel, plus 4 TTL alarm outputs

Get the next-generation data acquisition (DAQ) system with a 3-slot mainframe and your choice of 9 plug-in modules. Interface with the DAQ using Keysight BenchVue DAQ software, the intuitive graphical front panel with task oriented, self-guiding menus, or a web browser.

• Advanced 6½ digit internal DMM with improved accuracy and faster measurement speed
• Ability to measure very low current ranges (1 μA DC and 100 μA AC) and higher resistance range (1000 M?)
• New auto-calibration that compensates for internal drifts caused by time and temperature changes
• 3497XA compatible, program and configuration

Keysight’s BenchVue DAQ Control and Analysis app is available for use with the DAQ970A, DAQ973A, 34970A, 34972A and 34980A. BenchVue gives you an intuitive interface for test configuration and real-time data display and analysis. Setup and make measurements quickly, export data or log and view real-time measurements with a variety of display types to interpret your data faster. BenchVue Software also supports many other Keysight instruments giving you a single interface for Keysight’s most popular instruments.

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• Keysight DAQ973A Data sheet
• Keysight DAQ973A User Manual

• Remote Head for M8045A Pattern Generator
• 1 Channel

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• Data rates 150 Mb/s to 7 Gb/s or to 12.5 Gb/s pattern generator and error detector. Option to extended data rate to 14.2 Gb/s for pattern generator.
• >0.5 UI calibrated, compliant and integrated jitter injection: RJ, RJ-LF, RJ-HF, PJ1, PJ2, SJ, BUJ, ISI, sinusoidal interference, triangular and arbitrary SSC and residual SSC
• Excellent signal performance and sensitivity
• Built-in clock data recovery with tunable and compliant loop bandwidth
• Half-rate clocking with variable duty cycle for forwarded clocked devices
• Measures BER, BERT Scan, TJ with RJ/DJ separation, eye diagram, eye mask, BER contour, automated jitter tolerance, pattern capture, frame error rate (FER), or symbol error rate (SER) coded and retimed data streams
• Two adjustable data outputs with independent PRBS and pattern with 120 block pattern sequencer
• All options are retrofittable and upgrade from N4903A possible

The J-BERT N4903B high-performance serial BERT provides the most complete jitter tolerance test for embedded and forward clocked devices.

It is the ideal choice for R&D and validation teams characterizing and stressing chips and transceiver modules that have serial I/O ports up to 7 Gb/s, 12.5Gb/s or 14.2 Gb/s. It can characterize a receiver’s jitter tolerance and is designed to prove compliance to today’s most popular serial bus standards, such as:

• PCI Express® 
• SATA/SAS
• DisplayPort
• USB SuperSpeed
• Fibre Channel
• QPI
• Memory buses, such as fully buffered DIMM2
• Backplanes, such as CEI
• 10 GbE/ XAUI
• XFP/XFI, SFP+

Accurate characterization is achieved with clean signals from the pattern generator, which features exceptionally low jitter and extremely fast transition times. Built-in and calibrated jitter source allow accurate jitter tolerance testing of receivers.

Test set-up is simplified significantly, because the J-BERT N4903B is designed to match serial bus standards optimally with its differential I/Os, variable voltage levels on most outputs, built-in jitter and ISI, pattern sequencer, reference clock outputs, tunable CDR, pattern capture and bit recovery mode to analyze clock-less and non-deterministic patterns.SER/FER analysis allows jitter tolerance testing of devices using retimed loopback. A second data output with independent pattern memory and PRBS can be used as aggressor channel for crosstalk tests, or when adding channels externally for OOB timing tests or emulation of 3-level signals or signal de-emphasis.

Faster test execution is possible with J-BERT’s automated jitter tolerance tests fast total jitter measurements.

The J-BERT N4903B is a long-term investment which is configurable for today’s test and budget requirements but also allows upgrades from the N4903A model, and later retrofit of all options and full speed when test needs change.

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• Keysight N4903B-C13 Data sheet
• Keysight N4903B-C13 User Manual

• Data rates 150 Mb/s to 7 Gb/s or to 12.5 Gb/s pattern generator and error detector. Option to extended data rate to 14.2 Gb/s for pattern generator.
• >0.5 UI calibrated, compliant and integrated jitter injection: RJ, RJ-LF, RJ-HF, PJ1, PJ2, SJ, BUJ, ISI, sinusoidal interference, triangular and arbitrary SSC and residual SSC
• Excellent signal performance and sensitivity
• Built-in clock data recovery with tunable and compliant loop bandwidth
• Half-rate clocking with variable duty cycle for forwarded clocked devices
• Measures BER, BERT Scan, TJ with RJ/DJ separation, eye diagram, eye mask, BER contour, automated jitter tolerance, pattern capture, frame error rate (FER), or symbol error rate (SER) coded and retimed data streams
• Two adjustable data outputs with independent PRBS and pattern with 120 block pattern sequencer
• All options are retrofittable and upgrade from N4903A possible

The J-BERT N4903B high-performance serial BERT provides the most complete jitter tolerance test for embedded and forward clocked devices.

It is the ideal choice for R&D and validation teams characterizing and stressing chips and transceiver modules that have serial I/O ports up to 7 Gb/s, 12.5Gb/s or 14.2 Gb/s. It can characterize a receiver’s jitter tolerance and is designed to prove compliance to today’s most popular serial bus standards, such as:

• PCI Express® 
• SATA/SAS
• DisplayPort
• USB SuperSpeed
• Fibre Channel
• QPI
• Memory buses, such as fully buffered DIMM2
• Backplanes, such as CEI
• 10 GbE/ XAUI
• XFP/XFI, SFP+

Accurate characterization is achieved with clean signals from the pattern generator, which features exceptionally low jitter and extremely fast transition times. Built-in and calibrated jitter source allow accurate jitter tolerance testing of receivers.

Test set-up is simplified significantly, because the J-BERT N4903B is designed to match serial bus standards optimally with its differential I/Os, variable voltage levels on most outputs, built-in jitter and ISI, pattern sequencer, reference clock outputs, tunable CDR, pattern capture and bit recovery mode to analyze clock-less and non-deterministic patterns.SER/FER analysis allows jitter tolerance testing of devices using retimed loopback. A second data output with independent pattern memory and PRBS can be used as aggressor channel for crosstalk tests, or when adding channels externally for OOB timing tests or emulation of 3-level signals or signal de-emphasis.

Faster test execution is possible with J-BERT’s automated jitter tolerance tests fast total jitter measurements.

The J-BERT N4903B is a long-term investment which is configurable for today’s test and budget requirements but also allows upgrades from the N4903A model, and later retrofit of all options and full speed when test needs change.

Adding options and accessories may impact shipping times

Request a customized version of this model by requesting a Custom Quote

• Keysight N4903B-C13 Data sheet
• Keysight N4903B-C13 User Manual

• Adjustable de-emphasis for one pre- and 2 post-cursors of 0 to 12 dB
• Supports data rates from 660 Mb/s to 14.2 Gb/s
• Tolerates non-balanced patterns
• Transparent to jitter
• Flexible usage as front-end for J-BERT N4903B, ParBERT 81250A or other pattern generators
• Optional Clock Multiplier(opt. 001)
• Small size
• Programmable via J-BERT N4903B or stand-alone

Why is signal de-emphasis needed?

The de-emphasis technique is used in the transmission of digital electrical signals at gigabit data rates. De-emphasis is a signal pre-distortion to compensate for signal degradations that occur when transmitting electrical signals with gigabit rates over PC board traces, backplanes, or long cables. With the next generation of serial bus standards operating above 5 Gb/s, sophisticated de-emphasis with multi-tap Finite Impulse Response (FIR) filtering will be needed.

Many popular high-speed digital interfaces use de-emphasis, such as PCI Express®, SATA, USB3, QPI, IEEE 802.3 backplanes (10GBASE-KR, 40GBASE-KR4).

What does the N4916B offer?

The new N4916B de-emphasis signal converter enables R&D and test engineers to accurately emulate transmitter de-emphasis.

The N4916B can emulate transmitter de-emphasis with one pre- and two post-cursors and individually adjustable de-emphasis levels of up to 12.0 dB. With its DC-coupling it tolerates unbalanced pattern streams that often occur in training sequences. The N4916B is designed to be transparent to jitter when stimulated with jitter on data and clock signal, enabling emulation of real-world de-emphasis and jitter conditions that a receiver is expected to tolerate. De-emphasis can also be used to compensate for distortions caused by cables, fixtures or test boards in the test set for more precise device characterization results.

The new De-emphasis Signal Converter can be used as front-end for J-BERT N4903B, ParBERT or other gigabit pattern generators. It is controlled via its USB interface from the J-BERT N4903B user interface or from a stand-alone user interface with programming examples.

What does the the clock multiplying option of N4916B offer?

The clock multiplier option enables error counting and error analysis of devices using half-rate clocking. The full-rate clock is needed to use the error, eye or jitter analysis capabilities of J-BERT N4903B.

What are the key differences to N4916A?

• 3 adjustable cursors (N4916A has one post-cursor, sufficient for data rates < 5 Gb/s)
• Optional clock multiplier
• Stand-alone user interface
• Maximum data rate
• Aligned data and clock input signals are required with N4916B for full jitter transparency
• Size

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• Keysight N4916B Data sheet
• Keysight N4916B User Manual

Features

• 1 to 12.5 Gb/s Pattern Generator remote head
• Integrated two-tap or four-tap de-emphasis signal conditioning
• Programmable generator output parameters
• Transparent jitter pass-through
• Remote head allows placement of signal very close to DUT

Compatibility

• N4965A Multi-Channel BERT 12.5 Gb/s

The N4955A is an affordable and compact pattern generator remote head available in two-tap and four-tap de-emphasis configurations. Compatible with the N4965A Serial BERT controller, it is an ideal solution to test up to 12.5 Gb/s per channel for characterizing multi-lane serial data channels. The N4955A pattern generator supports PRBS, clock, and DC logic patterns and operates up to 12.5 Gb/s with differential of single-ended connections. The remote head allows the test equipment to be located very close to the device under test, eliminating the need for long cables that degrade signal quality.

Applications:

• Serial data receiver characterization up to 12.5 Gb/s
• Multi-lane device characterization
• Crosstalk characterization

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• Keysight N4955A-D12 Data sheet
• Keysight N4955A-D12 User Manual

The Keysight N4962A is a cost-effective 10G BERT, consisting of an internal clock system, PRBS generator, and error detector. It is designed for automated production-line testing, manufacturing, and characterization. The N4962A instrument features highly integrated custom ASICs, which lower part count and operating temperature, resulting in high reliability. The N4962A is also compact with a simple interface, making it ideal for use on a production test bench.

Features

• Internal clock synthesizer for 9.90 to 11.35 Gb/s operation
• 0.5 to 12.5 Gb/s operation with external clock
• Multiple clock and pattern triggers
• Programmable output amplitude control
• Selectable PRBS pattern length, mark-space density
• Local push-button and GPIB remote interface

Applications

• 10G and lower rate optical transceiver production test
• Communication component incoming inspection
• General 10G device characterization

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• Keysight N4962A Data sheet
• Keysight N4962A User Manual

Features

• Operation from 3.5 to 44 Gb/s
• Demux-by-2 or demux-by-4
• Integrated phase shifter for high-speed clock and data alignment
• Differential or single-ended input
• Adjustable sub-rate clock output

The Keysight Technologies N4968A clock and data demultiplexer 44 Gb/s is a small high-performance 3.5 to 44 Gb/s clock and data demultiplexer, designed to simplify the process of making high-bitrate BER measurements at half- or quarter-rate speeds. The N4968A clock and data demultiplexer 44 Gb/s is capable of operating in demux-by-2 (17 to 8.5 Gb/s) or demux-by-4 (38 to 9.5 Gb/s) modes, with an adjustable sub-rate clock output for triggering BER testers, oscilloscopes, logic analyzers, or other instruments.

Applications

• OC-768/STM-256
• 100G Ethernet (4 x 25.78 Gb/s)
• High bit rate research

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• Keysight N4968A Data sheet
• Keysight N4968A User Manual